1. Field
Example embodiments relate to semiconductor devices and methods of fabricating the same. Other example embodiments relate to semiconductor devices having through vias and methods of fabricating the same.
2. Description of the Related Art
A technique for more densely packaging semiconductor devices has been increasingly demanded with the development of lighter, smaller, faster, and improved performance in more sophisticated electronic products. In response to such a demand, packaging techniques (e.g., assembly techniques) for three dimensionally stacking semiconductor chips have been proposed. For example, a technique for electrically connecting a plurality of semiconductor chips stacked on a board with use of through vias has been employed in a semiconductor assembly process.
The through vias may be mainly formed in scribe lanes of the respective semiconductor chips, and the through vias may be electrically connected to input/output (I/O) pads of the corresponding semiconductor chip via redistributed interconnections. The scribe lanes may be wider than the width of the through vias. However, the area that the scribe lanes occupy may be reduced in order to increase the number of the semiconductor chips at a wafer level. In addition, a sawing technique for separating the semiconductor chips formed on a single wafer from one another has been improved. The improved sawing technique allows a reduction of the width of the scribe lane.
However, there may be a limitation in reducing the width of the scribe lanes when the through vias penetrating the scribe lanes are used. For example, if the I/O pads of the semiconductor chips are disposed at a central region of the semiconductor chips, employing the through vias formed in the scribe lanes may be difficult. Relatively long redistributed interconnections may be required to electrically connect the I/O pads to the through vias and the relatively long redistributed interconnections may cause malfunction of the semiconductor chips due to parasitic capacitance or inductance thereof.
FIGS. 1A to 1D are cross sectional views illustrating a conventional method of fabricating a semiconductor device having through vias. Referring to FIG. 1A, a semiconductor chip 10 may include a wafer 11 which is composed of semiconductor elements, e.g., silicon. An insulating layer 13 may be formed on a top surface 11a of the wafer 11, and an input/output (I/O) pad 15 may be formed on the insulating layer 13. Patterns (not shown) constituting internal circuits may be formed in the insulating layer 13. A passivation layer 17 may be formed on the insulating layer 13 to protect the internal circuit and a portion of the I/O pad 15 from an external environment. The I/O pad 15, the insulating layer 13 and the wafer 11 may be etched to form a hole 19 in the wafer 11. The hole 19 may penetrate the I/O pad 15 and the insulating layer 13.
Referring to FIG. 1B, a hole insulating layer 21 may be formed on an inner wall 19a of the hole 19, and an electrode 25 may be formed to fill the hole 19 which is surrounded by the hole insulating layer 21. The electrode 25 may be configured to connect to the I/O pad 15 even though it is not shown in FIG. 1B. A base layer 23 may be formed on the hole insulating layer 21 prior to formation of the electrode 25. The base layer 23 may include a barrier layer and/or a seed layer.
Referring to FIG. 1C, a lower portion of the wafer 11 may be removed such that a lower portion 25b of the electrode 25 may protrude from a bottom surface 11b of the wafer 11. The electrode 25 may completely penetrate the wafer 11, thereby acting as a through via. The conventional method described above may exhibit some disadvantages, as illustrated in FIG. 1D.
Referring to FIG. 1D, fragments of the wafer 11 may be generated during formation of the hole 19, and the fragments of the wafer 11 may adhere onto the I/O pad 15 along the sidewall 19a of the hole 19. A layer 12 composed of the fragments may be formed on the sidewall 19a of the hole 19. Accordingly, even though the hole insulating layer 21 is formed on the sidewall 19a of the hole 19, the I/O pad 15 may be electrically connected to the wafer 11 through the layer 12. In other words, electrical shortage between the I/O pad 15 and the wafer 11 may occur due to a silicon splash phenomenon during formation of the hole 19.